https://www.digchip.com/datasheets/download_datasheet.php?id=1901061&part-number=93C56
93C56.pdfDESCRIPTION
The Microchip Technology Inc.
93C56A/B is a 2K-bit, low-voltage serial Electrically Erasable PROM.
93C56 칩은 2K-bit, 저전압 시리얼 PROM이다.
The device memory is configured as 256 x 8 bits (93C56A) or 128 x 16 bits (93C56B). Advanced CMOS technology makes this device ideal for low-power, nonvolatile memory applications.
이 디바이스 메모리는 구성되있다. as 256x8 bit들로 or 128x16 bit들로.
진보된 CMOS기술은 만든다. 이 device를 이상적으로 for 저전압을 위해, 비 휘발성 memory applications를.
The 93C56A/B is available in standard 8-pin DIP and surface mount SOIC packages.
This device is only recommeded for 5V automotive temperature applications.
For all commercial and industrial applications, the 93LC56A/B is recommended.
For 모든 상업용 and 공장용 applications를 위해, the 93LC56A가 추천된다.
2.0 PIN DESCRIPTION
2.1 Chip Select (CS)
A high level selects the device.
A low level deselects the device
and
forces it into standby mode.
However, a programming cycle which is already in progress
will be completed,
regardless of the CS input signal.
High Level은 칩을 선택하고
Low Level은 칩선택을 취소한다.
and
강제로 돌아간다. into stanby모드로.
하지만, a 프로그래밍사이클... which is already in progress상태에 있는
...은 will be completed된다,
상관없이 of the CS 입력 신호에.
If CS is brought low during a program cycle,
the device will go into standby mode as soon as the programming cycle is completed.
CS must be low for 250 ns minimum (TCSL) between consecutive instructions.
If CS is low, the internal control logic is held in a RESET status.
만약 CS가 갖고오게된다면 LOW를 dring a programming cycle에서,
the device는 will go into standby모드에 진입하게된다. as soon as the programming cycle이 끝나는대로.
(★programming cycle이 더큰 Priority를 갖고있다. But P-Cycle이 한차례 끝난후 CS상태를 신경쓴다.)
CS는 반드시 be LOW가 되야한다. for 250ns 동안 between 연속적인 지시들 사이에서
If CS가 LOW가되면, the 내부 컨트롤 logic은 held in a RESET 상태에 고정된다.
2.2 Serial Clock (CLK)
The Serial Clock is used to synchronize the communication
between a master device and the 93C56A/B.
Opcode, address, and data bits are clocked in on the positive edge of CLK. Data bits are also clocked out on the positive edge of CLK. CLK can be stopped anywhere in the transmission sequence (at high or low level) and can be continued anytime with respect to clock high time (TCKH) and clock low time (TCKL).
This gives the controlling master freedom in preparing opcode, address, and data. CLK is a “Don't Care” if CS is low (device deselected).
If CS is high, but the START condition has not been detected, any number of clock cycles can be received by the device without changing its status (i.e., waiting for a START condition).
CLK cycles are not required during the self-timed WRITE (i.e., auto ERASE/WRITE) cycle. After detecting a START condition, the specified number of clock cycles (respectively low to high transitions of CLK) must be provided. These clock cycles are required to clock in all required opcode, address, and data bits before an instruction is executed (Table 2-1 and Table 2-2). CLK and DI then become don't care inputs waiting for a new START condition to be detected.
2.3 Data In (DI) Data In is used to clock in a START bit, opcode, address, and data synchronously with the CLK input.
2.4 Data Out (DO) Data Out is used in the READ mode to output data synchronously with the CLK input (TPD after the positive edge of CLK). This pin also provides READY/BUSY status information during ERASE and WRITE cycles. READY/BUSY status information is available on the DO pin if CS is brought high after being low for minimum chip select low time (TCSL) and an ERASE or WRITE operation has been initiated. The status signal is not available on DO, if CS is held low during the entire ERASE or WRITE cycle. In this case, DO is in the HIGH-Z mode. If status is checked after the ERASE/WRITE cycle, the data line will be high to indicate the device is ready
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